Added CEP 2 Cores 2 & 5
Added CEP 2 Cores 2 & 5
This commit is contained in:
30
cep2_core5/zlc_s73.pwk
Normal file
30
cep2_core5/zlc_s73.pwk
Normal file
@@ -0,0 +1,30 @@
|
||||
#Exported from 3ds max by MDL Plug-in Suite 1.0b
|
||||
#http://www.bricksbuilder.com/nwn/utils/
|
||||
#MAXMODEL ASCII
|
||||
# model: PLC_Rok
|
||||
filedependancy Rock01.max
|
||||
node trimesh zlc_s73_wg
|
||||
parent zlc_s73_pwk
|
||||
position -0.155427 0 0
|
||||
orientation 0 0 0 0
|
||||
wirecolor 0.878906 0.878906 0.878906
|
||||
ambient 1 1 1
|
||||
diffuse 1 1 1
|
||||
specular 0 0 0
|
||||
shininess 1
|
||||
bitmap PLC_RugDMtlBrk
|
||||
verts 4
|
||||
-0.169358 -0.358812 0
|
||||
0.480217 -0.358812 0
|
||||
-0.169357 0.42085 0
|
||||
0.480217 0.42085 0
|
||||
faces 2
|
||||
2 0 3 1 0 0 0 7
|
||||
1 3 0 1 0 0 0 7
|
||||
endnode
|
||||
node dummy s73_pwk_use01
|
||||
parent zlc_s73_pwk
|
||||
position 0.00216713 -0.349336 0
|
||||
orientation 0 0 0 0
|
||||
wirecolor 0.878906 0.878906 0.878906
|
||||
endnode
|
||||
Reference in New Issue
Block a user