Added CEP 2 Cores 2 & 5
Added CEP 2 Cores 2 & 5
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24
cep2_core5/zlc_vv2.pwk
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24
cep2_core5/zlc_vv2.pwk
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#MAXDOOR ASCII
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# model: vpl_portal01_PWK
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filedependancy vpl_portal01.max
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node trimesh zlc_vv2_wg
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parent zlc_vv2_pwk
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position -0.8 0.0 0.0
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orientation 0.0 0.0 0.0 0.0
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wirecolor 0.52549 0.0235294 0.0235294
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bitmap NULL
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verts 8
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-0.15 -0.15 0.0
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0.15 -0.15 0.0
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-0.15 0.15 0.0
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0.15 0.15 0.0
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1.45 -0.15 0.0
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1.75 -0.15 0.0
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1.45 0.15 0.0
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1.75 0.15 0.0
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faces 4
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2 0 3 1 0 0 0 1
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1 3 0 1 0 0 0 1
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6 4 7 1 0 0 0 1
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5 7 4 1 0 0 0 1
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endnode
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