Added CEP 2 Cores 2 & 5
Added CEP 2 Cores 2 & 5
This commit is contained in:
39
cep2_core5/zlc_vv3.pwk
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39
cep2_core5/zlc_vv3.pwk
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#MAXDOOR ASCII
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# model: vpl_strange01_PWK
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filedependancy vpl_strange01.max
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node trimesh zlc_vv3_wg
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parent zlc_vv3_pwk
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position 0.03961 0.0 0.0
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orientation 0.0 0.0 0.0 0.0
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wirecolor 0.6 0.894118 0.839216
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bitmap NULL
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verts 8
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0.8 0.0 0.829346
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0.498792 0.625465 0.829346
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-0.178017 0.779942 0.829346
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-0.720775 0.347107 0.829346
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-0.720775 -0.347107 0.829346
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-0.178017 -0.779942 0.829346
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0.498792 -0.625465 0.829346
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0.0 0.0 0.829346
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faces 7
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7 0 1 1 0 0 0 1
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7 1 2 1 0 0 0 1
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7 2 3 1 0 0 0 1
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7 3 4 1 0 0 0 1
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7 4 5 1 0 0 0 1
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7 5 6 1 0 0 0 1
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7 6 0 1 0 0 0 1
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endnode
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node dummy vv3_pwk_use02
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parent zlc_vv3_pwk
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position -0.00100983 -0.814796 0.0
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orientation 0.0 0.0 0.0 0.0
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wirecolor 0.694118 0.580392 0.101961
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endnode
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node dummy vv3_pwk_use01
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parent zlc_vv3_pwk
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position -0.00100983 0.776829 0.0
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orientation 0.0 0.0 0.0 0.0
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wirecolor 0.694118 0.580392 0.101961
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endnode
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